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PE43702
Product Specification
Figure 15. Serial Timing Diagram
Bits can either be set to logic high or logic low
D[7] must be set to logic low
DI[6:0]
P/S
T DISU
T PSSU
T DIH
T PSIH
SI
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
CLK
T SISU
T SIH
LE
T CLKL
T CLKH
T LESU
DO[6:0]
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
T LEPW
T PD
VALID
DI[6:0]
T PSSU
VALID
T PSH
LE
DO[6:0]
T DISU
T LEPW
T DIPD
VALID
T PD
T DIH
Table 10. Serial Interface AC Characteristics
V DD = 3.3 or 5.0 V, -40° C < T A < 85° C, unless otherwise specified
Table 11. Parallel and Direct Interface AC
Characteristics
Symbol
Parameter
Min
Max
Unit
V DD = 3.3 or 5.0 V, -40° C < T A < 85° C, unless otherwise specified
F CLK
T CLKH
T CLKL
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
-
30
30
10
-
-
MHz
ns
ns
Symbol
T LEPW
Parameter
Latch Enable minimum
pulse width
Min
30
Max
-
Unit
ns
Last serial clock rising edge
T DISU
Parallel data setup time
100
-
ns
T LESU
T LEPW
T SISU
T SIH
T DISU
T DIH
setup time to Latch Enable
rising edge
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
10
30
10
10
100
100
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
T DIH
T PSSU
T PSIH
T PD
T DIPD
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
100
100
100
-
-
-
-
-
10
5
ns
ns
ns
ns
ns
T ASU
T AH
T PSSU
T PSH
T PD
Address setup time
Address hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
100
100
100
100
-
-
-
-
-
10
ns
ns
ns
ns
ns
Document No. 70-0244-04 │ www.psemi.com
?2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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